ALIEN - Abstraction Layer for Implementation of Extensions in programmable Networks
Duration
01.10.2012 - 30.09.2014Financing entity
European Union's Research and Innovation funding programme - FP7Summary
Project ALIEN (Abstraction Layer for Implementation of Extensions in programmable Networks) fits well into the world trend of research on SDN (Software Defined Networking), aimed at putting this solution into practice as soon as possible. SDN networks separate the planes of data and control, with the control being administered by a central controller that communicates with switches/routers via a communication protocol. Devices connected to an SDN network must cooperate with the controller and respond to its instructions. Currently, one of the most developed protocols used in the implementation of SDN networks is OpenFlow. Starting an SDN network with the OpenFlow protocol would require replacing the network equipment with devices supporting this protocol. Modernization of network infrastructure in which devices natively compliant with OpenFlow and devices without mechanisms supporting this protocol could coexist causes numerous problems with its operation and management, and increases the cost of maintenance. Therefore, one should aim at developing a homogeneous structure (from the point of view of OpenFlow-based control) in an evolutionary way, without raising the cost of network maintenance.The chief goal of the ALIEN project has been the design, implementation on selected devices, and testing of the Hardware Abstraction Layer (HAL). This layer ensures the possibility of simultaneous control of packet flow, according to SDN mechanisms, in a network composed of native OpenFlow devices and non-native OpenFlow devices controlled via HAL. The new solutions have been tested using an SDN infrastructure built within the framework of the OFELIA project.
Devices not supporting OpenFlow include: standard network switches, optical switches, EPON devices (Ethernet Passive Optical Network), packet processing an monitoring devices, such as FPGA (Field Programmable Gate Array) cards, network processors, CATV (Cable TV) devices, e.g., HFC (Hybrid Fibre-Coaxial) modems, etc. In the ALIEN project, HAL has been designed and implemented for the following devices: NetFPGA cards, EZappliance platform with EZChip NP-3 network processors, Cavium OCTEON Plus AMC network processors used in ATCA systems, optical switches, elements of GEPON (Gigabit Ethernet Passive Optical Network), such as OLT (Optical Line Termination) and ONU (Optical Network Unit), and DOCSIS (Data Over Cable Service Interface Specification) devices.
Goals pursued within the project framework may be described as follows:
- Defining the HAL abstraction layer that enables OpenFlow-based control of devices that natively do not support this protocol, called non-OpenFlow devices. The layer provides homogeneous interfaces that enable communication with non-OpenFlow devices and identification of their properties.
- Implementation of the proposed HAL-based solutions in selected non-OpenFlow devices. The software has been designed and built in modules in order to separate the main module for OpenFlow support and device-specific controllers communicating with network equipment.
- Integration of devices controlled with the aid of HAL with SDN infrastructure built in the OFELIA project (OpenFlow network). The integration took into account the current requirements of the management system used in the OFELIA project and the possibilities of non-OpenFlow devices.
- Verification of the implemented solutions in experiments conducted using the test infrastructure from the OFELIA project. The experiments demonstrated the possibilities and confirmed the sensibility of using non-OpenFlow devices controlled via HAL. Each experiment was conducted according to the principles of controlling the SDN networks implemented in the OFELIA project network. The experiments employed, e.g., scenarios connected with the operation of Content-Centric Networking (CCN).
- Dissemination of the obtained results through various publications and arousing the interest of standardization bodies in the studied problem. This mainly pertains to the integration of activities pursued in different projects concerning issues in SDN networks and Future Internet architectures.
Publications, reports or patents resulting from the project
| 01. | G. Danilewicz, M. Dziuba, J. Kleban, M. Michalski, R. Rajewski, M. Żal, B. Belter, A. Binczewski, Ł. Ogrodowczyk, D. Parniewicz and M. Stroiński, “Projekt ALIEN – Warstwa Abstrakcji Dla Urządzeń Non-Openflow w Sieciach SDN,” Krajowe Sympozjum Telekomunikacji i Teleinformatyki, KSTiT 2014, Poznań 03-05 Sep. 2014., Przegląd Telekomunikacyjny i Wiadomości Telekomunikacyjne, vol. 8-9, pp. 1297-1304, 2014. |
| 02. | M. Michalski and T. Sielach, “Implementacja modułu kart NetFPGA1G i NetFPGA10G w xDPd,” Krajowe Sympozjum Telekomunikacji i Teleinformatyki, KSTiT 2014, Poznań 03-05 Sep. 2014., Przegląd Telekomunikacyjny i Wiadomości Telekomunikacyjne, vol. 8-9, pp. 1305-1312, 2014. |
| 03. | G. Danilewicz, M. Dziuba, J. Kleban, M. Michalski, R. Rajewski, M. Żal,A. Binczewski, K. Dombek, A. Juszczyk, Ł.Ogrodowczyk, I. Olszewski, D. Parniewicz and M. Stroiński, “ALIEN Project - Abstraction Layer for Implementation of Extensions in programmable Network,” IEICE Information and Communication Technology Forum 2014 (ICTF), Poznań 28-30 May. 2014. |
| 04. | M. Michalski and T. Sielach, “Adding Support for NetFPGA10G Cards in xDPd,” IEICE Information and Communication Technology Forum 2014 (ICTF), Poznań 28-30 May. 2014. |
| 05. | Ł. Ogrodowczyk, B. Belter, A. Binczewski, K. Dombek, A. Juszczyk, I. Olszewski, D. Parniewicz, R. Doriguzzi Corin, M. Gerola, E. Salvadori, K. Pentikousis, U. Toseef, H. Woesner, M. Rashidi Fard, M. Huarte, E. Jacob, J. Matias, V. Fuentes, M. Michalski, and R. Rajewski, “Hardware Abstraction Layer for Non-OpenFlow Capable Devices,” in Proc. ofTERENA Networking Conference 2014 (TNC2014), Dublin, Irleand, 19 - 22 May 2014. |
| 06. | Deliverable D2.1 - Report on Hardware abstraction models, stan z 10.03.2014 [PDF] |
| 07. | Deliverable D3.1 - Hardware platforms and switching constraints, stan z 10.03.2014 [PDF] |
| 08. | Deliverable D3.2 - Specification of Hardware Specific Parts, stan z 10.03.2014 [PDF] |
| 09. | Deliverable D2.2 - Specification of Hardware Abstraction Layer, stan z 30.10.2014 [PDF] |
| 10. | DDeliverable D2.3 - Report on Implementa on of the Common Part of an OpenFlow Datapath Element and the Extended FlowVisor, stan z 30.10.2014 [PDF] |
| 11. | Deliverable D3.2 - Specification of Hardware Specific Parts, stan z 30.10.2014 [PDF] |
| 12. | Deliverable D3.3 - Final Prototypes of Hardware Specific Parts, stan z 30.10.2014 [PDF] |
| 13. | Deliverable D5.2 - CCN and ALIEN developments integration over OFELIA, stan z 30.10.2014 [PDF] |
| 14. | Deliverable D5.3 - Experimentation results and reporting activitie, stan z 30.10.2014 [PDF] |
Supervisor/Coordinator
Poznańskie Centrum Superkomputerowo SiecioweProject Manager (PUT)
dr hab. inż. Grzegorz Danilewicz, prof. nadzw.Project participants (PUT)
dr hab. inż. Grzegorz Danilewicz, prof. nadzw.dr inż. Janusz Kleban
dr inż. Marek Michalski
dr hab. inż. Mariusz Żal
dr inż. Remigiusz Rajewski
Marcin Dziuba